搜索资源列表
RS232.VHDL
- RS232 Communication function in VHDL for Spartan 3E
rs232
- rs232 interface for xilinx spartan 3e
Xil3S500E_revD_emac
- spartan 3e开发板中实现以太网通讯-spartan 3e development board Ethernet communications
1024FFT-verilog-hdl
- 基于spartan 3e 的IFFT算法verilog HDL程序-Based on the verilog 3e Spartan IFFT algorithm of HDL program
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro
Spartan3EStarteKiBoardUserGuide
- Spartan-3E Starte KiBoardUserGuide，xilinx入门开发板的说明书，提供了部分代码-Spartan-3E Starte KiBoardUserGuide, xilinx entry specification development board to provide some code
uClinux_Spartan_3E_Starter
- How to set up uCLinux on the Spartan 3E starter platform
bare_vga
- Vga in vhdl using spartan 3e board basys
FPGA_SPI_FLASH
- 本应用指南讲述 Spartan-3E 系列中的串行外设接口 (SPI) 配置模式。SPI 配置模式拓宽了 SpartanTM-3E 设计人员可以使用的配置解决方案。SPI Flash 存储器件引脚少、封装外形小而 且货源广泛。本指南讨论用 SPI Flash 存储器件配置 Spartan-3E FPGA 所需的连接，并且介绍 SPI 模式的配置流程。本指南还提供一种实用工具，用于在原型开发过程中对选定的 STMicroelectronics 和 Atmel SPI 器件进
P2S
- This file is used to transfer p2s data in a Spartan 3e
DieuKhienLED
- Shift LED on Spartan 3E kit board.
Fingerprint_Identify
- 本项目名称是：基于FPGA的指纹识别模块设计。 主要内容为：本模块采用xilinx公司的Spartan 3E系列XC3S500E 型FPGA作为核心控制芯片，通过富士通公司的MFS300滑动式电容指纹传感器对指纹图象进行提取，然后对提取的指纹图像进行灰度滤波、图像增强、二值化、二值去噪、细化等预处理，得到清晰的指纹图象，再从清晰的指纹图象中提取指纹特征点，存入外部FLASH作为建档模板。指纹比对时，采用同样的方法获得清晰的指纹图像，建立比对模板，然后将比对模板与建档模板利用点模式匹配
4559939-VGA-Video-Signal-Generation
- source code VGA for Xilinx FPGA Spartan 3E
eth_phy10
- an ethernet physique sender. it s implemented with spartan 3E starter kit
COMPRESSION
- Simple LZW image compression implemented on Spartan-3e starter kit using Xilinx9.2 and Modelsim for testbench simulation.
Spartan-3_NeuralNetwork_3-layer_feedforward_backp
- The aim of this project is the design and implementation of a system simulating a NN in the Spartan-3 Starter Board of Xilinx. The NN will be a 3-layer feedforward backpropagation.- The aim of this project is the design and implementation of
DDS
- A simple VHDL implementation of a DDS on Xilinx Spartan 3E Starter Kit development board
spartan_alu_8_bit
- Verilog based 8 bit ALU module, implemented on Spartan 3E FPGA.
MY_DDS
- 基于spartan-3e开发板的dds，包括串行通信的dac代码-direct digital frequency synthesis based on spartan-3e kitboard
DDS_FINAL
- My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different fre